NXP Semiconductors LPC1768 - ARM Cortex-M3 User Guide: Peripherals; About the Cortex-M3 Peripherals

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User manual Rev. 3 — 20 December 2013 760 of 841
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Chapter 34: Appendix: Cortex-M3 user guide
34.4 ARM Cortex-M3 User Guide: Peripherals
34.4.1 About the Cortex-M3 peripherals
The address map of the Private peripheral bus (PPB) is:
In register descriptions:
• the register type is described as follows:
–RW: Read and write.
–RO: Read-only.
–WO: Write-only.
• the required privilege gives the privilege level required to access the register, as
follows:
–Privileged: Only privileged software can access the register
– Unprivileged: Both unprivileged and privileged software can access the register.
Table 643. Core peripheral register regions
Address Core peripheral Description
0xE000E008 - 0xE000E00F System control block Table 654 “Summary of the
system control block registers”
0xE000E010 - 0xE000E01F System timer Table 674 “System timer registers
summary”
0xE000E100 - 0xE000E4EF Nested Vectored Interrupt
Controller
Table 644 “NVIC register
summary”
0xE000ED00 - 0xE000ED3F System control block Table 654 “Summary of the
system control block registers”
0xE000ED90 - 0xE000EDB8 Memory Protection Unit Table 680 “MPU registers
summary”
0xE000EF00 - 0xE000EF03 Nested Vectored Interrupt
Controller
Table 644 “NVIC register
summary”