UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 327 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
UART receiver DMA
In DMA mode, the receiver DMA request is asserted on the event of the receiver FIFO
level becoming equal to or greater than trigger level, or if a character time-out occurs. See
the description of the RX Trigger Level above. The receiver DMA request is cleared by the
DMA controller.
UART transmitter DMA
In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.
15.4.7 UART1 Line Control Register (U1LCR - 0x4001 000C)
The U1LCR determines the format of the data character that is to be transmitted or
received.
15.4.8 UART1 Modem Control Register (U1MCR - 0x4001 0010)
The U1MCR enables the modem loopback mode and controls the modem output signals.
Table 298: UART1 Line Control Register (U1LCR - address 0x4001 000C) bit description
Bit Symbol Value Description Reset Value
1:0 Word Length
Select
00 5-bit character length. 0
01 6-bit character length.
10 7-bit character length.
11 8-bit character length.
2 Stop Bit Select 0 1 stop bit. 0
1 2 stop bits (1.5 if U1LCR[1:0]=00).
3 Parity Enable 0 Disable parity generation and checking. 0
1 Enable parity generation and checking.
5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached
parity bit will be odd.
0
01 Even Parity. Number of 1s in the transmitted character and the attached
parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
6 Break Control 0 Disable break transmission. 0
1 Enable break transmission. Output pin UART1 TXD is forced to logic 0
when U1LCR[6] is active high.
7 Divisor Latch
Access Bit (DLAB)
0 Disable access to Divisor Latches. 0
1 Enable access to Divisor Latches.
31:8 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
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