NXP Semiconductors LPC1768 - Chapter 22: Lpc176 X;5 X Repetitive Interrupt Timer (RIT); Features; Description; Register Description

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User manual Rev. 3 — 19 December 2013 502 of 841
22.1 Features
• 32-bit counter running from PCLK. Counter can be free-running, or be reset by a
generated interrupt.
• 32-bit compare value.
• 32-bit compare mask. An interrupt is generated when the counter value equals the
compare value, after masking. This allows for combinations not possible with a simple
compare.
22.2 Description
The Repetitive Interrupt Timer provides a versatile means of generating interrupts at
specified time intervals, without using a standard timer. It is intended for repeating
interrupts that aren’t related to Operating System interrupts. However, it could be used as
an alternative to the Cortex-M3 System Tick Timer (Section 23.1
) if there are different
system requirements.
22.3 Register description
[1] Reset Value reflects the data stored in used bits only. It does not include content of reserved bits.
22.3.1 RI Compare Value register (RICOMPVAL - 0x400B 0000)
22.3.2 RI Mask register (RIMASK - 0x400B 0004)
UM10360
Chapter 22: LPC176x/5x Repetitive Interrupt Timer (RIT)
Rev. 3 — 19 December 2013 User manual
Table 433. Repetitive Interrupt Timer register map
Name Description Access Reset value
[1]
Address
RICOMPVAL Compare register R/W 0xFFFF FFFF 0x400B 0000
RIMASK Mask register. This register holds the 32-bit mask value. R/W 0 0x400B 0004
RICTRL Control register. R/W 0xC 0x400B 0008
RICOUNTER 32-bit counter R/W 0 0x400B 000C
Table 434. RI Compare Value register (RICOMPVAL - address 0x400B 0000) bit description
Bit Symbol Description Reset value
31:0 RICOMP Compare register. Holds the compare value which is compared to the counter. 0xFFFF FFFF
Table 435. RI Mask register (RIMASK - address 0x400B 0004) bit description
Bit Symbol Description Reset value
31:0 RIMASK Mask register. This register holds the 32-bit mask value. A one written to any bit overrides
the result of the comparison for the corresponding bit of the counter and compare register
(causes the comparison of the register bits to be always true).
0