UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 223 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
11.10.1.2 USB Clock Status register (USBClkSt - 0x5000 CFF8)
This register holds the clock availability status. The bits of this register are ORed together
to form the USB_NEED_CLK signal. When enabling a clock via USBClkCtrl, software
should poll the corresponding bit in USBClkSt. If it is set, then software can go ahead with
the register access. Software does not have to repeat this exercise for every access,
provided that the USBClkCtrl bits are not disturbed. USBClkSt is a read-only register.
11.10.2 Device interrupt registers
11.10.2.1 USB Interrupt Status register (USBIntSt - 0x5000 C1C0)
The USB Device Controller has three interrupt lines. This register allows software to
determine their status with a single read operation. All three interrupt lines are ORed
together to a single channel of the vectored interrupt controller. This register also contains
the USB_NEED_CLK status and EN_USB_INTS control bits. USBIntSt is a read/write
register.
3 - Reserved. User software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
4 AHB_CLK_EN AHB clock enable 0
31:5 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
Table 189. USBClkCtrl register (USBClkCtrl - address 0x5000 CFF4) bit description …continued
Bit Symbol Description Reset value
Table 190. USB Clock Status register (USBClkSt - address 0x5000 CFF8) bit description
Bit Symbol Description Reset value
0 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
1 DEV_CLK_ON Device clock on. The usbclk input to the device controller is active. 0
3:2 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
4 AHB_CLK_ON AHB clock on. 0
31:5 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description
Bit Symbol Description Reset value
0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read-only. 0
1 USB_INT_REQ_HP High priority interrupt line status. This bit is read-only. 0
2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only. 0
7:3 - These bits are reserved in a device-only configuration. User software should
not write ones to reserved bits. The value read from a reserved bit is not
defined. See Table 257
for OTG configuration.
NA
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