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User manual Rev. 3 — 19 December 2013 529 of 841
NXP Semiconductors
UM10360
Chapter 25: LPC176x/5x Motor control PWM
25.7.1.3 MCPWM Control clear address (MCCON_CLR - 0x400B 8008)
Writing ones to this write-only address clears the corresponding bits in MCCON.
25.7.2 MCPWM Capture Control register
25.7.2.1 MCPWM Capture Control read address (MCCAPCON - 0x400B 800C)
The MCCAPCON register controls detection of events on the MCI0-2 inputs for all
MCPWM channels. Any of the three MCI inputs can be used to trigger a capture event on
any or all of the three channels. This address is read-only, but the underlying register can
be modified by writing to addresses MCCAPCON_SET and MCCAPCON_CLR.
Table 457. MCPWM Control clear address (MCCON_CLR - 0x400B 8008) bit description
Bit Description
31:0 Writing ones to this address clears the corresponding bits in the MCCON register. See Table 455.
Table 458. MCPWM Capture Control read address (MCCAPCON - 0x400B 800C) bit description
Bit Symbol Description Reset
Value
0 CAP0MCI0_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0. 0
1 CAP0MCI0_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0. 0
2 CAP0MCI1_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1. 0
3 CAP0MCI1_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1. 0
4 CAP0MCI2_RE A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2. 0
5 CAP0MCI2_FE A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2. 0
6 CAP1MCI0_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0. 0
7 CAP1MCI0_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0. 0
8 CAP1MCI1_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1. 0
9 CAP1MCI1_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1. 0
10 CAP1MCI2_RE A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2. 0
11 CAP1MCI2_FE A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2. 0
12 CAP2MCI0_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0. 0
13 CAP2MCI0_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0. 0
14 CAP2MCI1_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1. 0
15 CAP2MCI1_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1. 0
16 CAP2MCI2_RE A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2. 0
17 CAP2MCI2_FE A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2. 0
18 RT0 If this bit is 1, TC0 is reset by a channel 0 capture event. 0
19 RT1 If this bit is 1, TC1 is reset by a channel 1 capture event. 0
20 RT2 If this bit is 1, TC2 is reset by a channel 2 capture event. 0
21 HNFCAP0 Hardware noise filter: if this bit is 1, channel 0 capture events are delayed as described in
Section 25.8.4
.
0
22 HNFCAP1 Hardware noise filter: if this bit is 1, channel 1 capture events are delayed as described in
Section 25.8.4
.
0
23 HNFCAP2 Hardware noise filter: if this bit is 1, channel 2 capture events are delayed as described in
Section 25.8.4
.
0
31:24 - Reserved. -
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