NXP Semiconductors LPC1768 - Register Description; USB Interrupt Status Register; 0 X5000 C1 C0)

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User manual Rev. 3 — 19 December 2013 278 of 841
NXP Semiconductors
UM10360
Chapter 13: LPC176x/5x USB OTG
13.8 Register description
The OTG and I
2
C registers are summarized in the following table.
The Device and Host registers are explained in Table 254
and Table 188 in the USB
Device Controller and USB Host (OHCI) Controller chapters. All registers are 32 bits wide
and aligned to word address boundaries.
13.8.1 USB Interrupt Status Register (USBIntSt - 0x5000 C1C0)
The USB OTG controller has seven interrupt lines. This register allows software to
determine their status with a single read operation.
The interrupt lines are ORed together to a single channel of the vectored interrupt
controller.
Remark: In a device-only configuration bits 6 to 3 of this register are reserved (see
Table 191
).
Table 256. USB OTG and I
2
C register address definitions
Name Description Access Reset value Address
Interrupt register
USBIntSt USB Interrupt Status R/W 0x8000 0100 0x400F C1C0
OTG registers
OTGIntSt OTG Interrupt Status RO 0 0x5000 C100
OTGIntEn OTG Interrupt Enable R/W 0 0x5000 C104
OTGIntSet OTG Interrupt Set WO NA 0x5000 C108
OTGIntClr OTG Interrupt Clear WO NA 0x5000 C10C
OTGStCtrl OTG Status and Control R/W 0 0x5000 C110
OTGTmr OTG Timer R/W 0xFFFF 0x5000 C114
I
2
C registers
I2C_RX I
2
C Receive RO NA 0x5000 C300
I2C_TX I
2
C Transmit WO NA 0x5000 C300
I2C_STS I
2
C Status RO 0x0A00 0x5000 C304
I2C_CTL I
2
C Control R/W 0 0x5000 C308
I2C_CLKHI I
2
C Clock High R/W 0xB9 0x5000 C30C
I2C_CLKLO I
2
C Clock Low WO 0xB9 0x5000 C310
Clock control registers
OTGClkCtrl OTG clock controller R/W 0 0x5000 CFF4
OTGClkSt OTG clock status RO 0 0x5000 CFF8
Table 257. USB Interrupt Status register - (USBIntSt - address 0x5000 C1C0) bit
description
Bit Symbol Description Reset
Value
0 USB_INT_REQ_LP Low priority interrupt line status. This bit is read-only. 0
1 USB_INT_REQ_HP High priority interrupt line status. This bit is read-only. 0
2 USB_INT_REQ_DMA DMA interrupt line status. This bit is read-only. 0