UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 39 of 841
NXP Semiconductors
UM10360
Chapter 4: LPC176x/5x Clocking and power control
4.5.5 PLL0 Status register (PLL0STAT - 0x400F C088)
The read-only PLL0STAT register provides the actual PLL0 parameters that are in effect
at the time it is read, as well as PLL0 status. PLL0STAT may disagree with values found in
PLL0CON and PLL0CFG because changes to those registers do not take effect until a
Table 21. Multiplier values for PLL0 with a 32 kHz input
Multiplier
(M)
Pre-divide
(N)
F
CCO
Multiplier
(M)
Pre-divide
(N)
F
CCO
4272 1 279.9698 12085 2 396.0013
4395 1 288.0307 12207 2 399.9990
4578 1 300.0238 12817 2 419.9875
4725 1 309.6576 12817 3 279.9916
4807 1 315.0316 13184 2 432.0133
5127 1 336.0031 13184 3 288.0089
5188 1 340.0008 13672 2 448.0041
5400 1 353.8944 13733 2 450.0029
5493 1 359.9892 13733 3 300.0020
5859 1 383.9754 13916 2 455.9995
6042 1 395.9685 14099 2 461.9960
6075 1 398.1312 14420 3 315.0097
6104 1 400.0317 14648 2 479.9857
6409 1 420.0202 15381 2 504.0046
6592 1 432.0133 15381 3 336.0031
6750 1 442.3680 15564 3 340.0008
6836 1 448.0041 15625 2 512.0000
6866 1 449.9702 15869 2 519.9954
6958 1 455.9995 16113 2 527.9908
7050 1 462.0288 16479 3 359.9892
7324 1 479.9857 17578 3 383.9973
7425 1 486.6048 18127 3 395.9904
7690 1 503.9718 18311 3 400.0099
7813 1 512.0328 19226 3 419.9984
7935 1 520.0282 19775 3 431.9915
8057 1 528.0236 20508 3 448.0041
8100 1 530.8416 20599 3 449.9920
8545 2 280.0026 20874 3 455.9995
8789 2 287.9980 21149 3 462.0070
9155 2 299.9910 21973 3 480.0075
9613 2 314.9988 23071 3 503.9937
10254 2 336.0031 23438 3 512.0109
10376 2 340.0008 23804 3 520.0063
10986 2 359.9892 24170 3 528.0017
11719 2 384.0082
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