UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 224 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
11.10.2.2 USB Device Interrupt Status register (USBDevIntSt - 0x5000 C200)
The USBDevIntSt register holds the status of each interrupt. A 0 indicates no interrupt and
1 indicates the presence of the interrupt. USBDevIntSt is a read-only register.
8 USB_NEED_CLK USB need clock indicator. This bit is set to 1 when USB activity or a change
of state on the USB data pins is detected, and it indicates that a PLL supplied
clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets
to zero 5 ms after the last packet has been received/sent, or 2 ms after the
Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from
0 to 1 can wake up the microcontroller if activity on the USB bus is selected
to wake up the part from the Power-down mode (see Section 4.8.8 “
Wake-up
from Reduced Power Modes” for details). Also see Section 4.5.9 “PLL0 and
Power-down mode” and Section 4.8.9 “Power Control for Peripherals
register (PCONP - 0x400F C0C4)” for considerations about the PLL and
invoking the Power-down mode. This bit is read-only.
1
30:9 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA
31 EN_USB_INTS Enable all USB interrupts. When this bit is cleared, the Vectored Interrupt
Controller does not see the ORed output of the USB interrupt lines.
1
Table 191. USB Interrupt Status register (USBIntSt - address 0x5000 C1C0) bit description …continued
Bit Symbol Description Reset value
Table 192. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit allocation
Reset value: 0x0000 0000
Bit 31 30 29 28 27 26 25 24
Symbol
--------
Bit 23 22 21 20 19 18 17 16
Symbol
--------
Bit 15 14 13 12 11 10 9 8
Symbol
------ERR_INTEP_RLZED
Bit 7 6 5 4 3 2 1 0
Symbol
TxENDPKT Rx
ENDPKT
CDFULL CCEMPTY DEV_STAT EP_SLOW EP_FAST FRAME
Table 193. USB Device Interrupt Status register (USBDevIntSt - address 0x5000 C200) bit description
Bit Symbol Description Reset value
0 FRAME The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers. 0
1 EP_FAST Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set,
the corresponding endpoint interrupt will be routed to this bit.
0
2 EP_SLOW Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is
not set, the corresponding endpoint interrupt will be routed to this bit.
0
3 DEV_STAT Set when USB Bus reset, USB suspend change or Connect change event occurs.
Refer to Section 11.12.6 “
Set Device Status (Command: 0xFE, Data: write 1 byte)” on
page 248.
0
4 CCEMPTY The command code register (USBCmdCode) is empty (New command can be written). 1
5 CDFULL Command data register (USBCmdData) is full (Data can be read now). 0
6 RxENDPKT The current packet in the endpoint buffer is transferred to the CPU. 0
7 TxENDPKT The number of data bytes transferred to the endpoint buffer equals the number of bytes
programmed in the TxPacket length register (USBTxPLen).
0
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