NXP Semiconductors LPC1768 - OTG Interrupt Set Register (Otgintset - 0 X5000 C20 C); OTG Interrupt Clear Register (Otgintclr - 0 X5000 C10 C); OTG Status and Control Register (Otgstctrl - 0 X5000 C110)

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User manual Rev. 3 — 19 December 2013 280 of 841
NXP Semiconductors
UM10360
Chapter 13: LPC176x/5x USB OTG
13.8.4 OTG Interrupt Set Register (OTGIntSet - 0x5000 C20C)
Writing a one to a bit in this register will set the corresponding bit in the OTGIntSt register.
Writing a zero has no effect. The bit allocation of OTGIntSet is the same as in OTGIntSt.
13.8.5 OTG Interrupt Clear Register (OTGIntClr - 0x5000 C10C)
Writing a one to a bit in this register will clear the corresponding bit in the OTGIntSt
register. Writing a zero has no effect. The bit allocation of OTGIntClr is the same as in
OTGIntSt.
13.8.6 OTG Status and Control Register (OTGStCtrl - 0x5000 C110)
The OTGStCtrl register allows enabling hardware tracking during the HNP hand over
sequence, controlling the OTG timer, monitoring the timer count, and controlling the
functions mapped to port U1 and U2.
Time critical events during the switching sequence are controlled by the OTG timer. The
timer can operate in two modes:
1. Monoshot mode: an interrupt is generated at the end of TIMEOUT_CNT (see
Section 13.8.7 “
OTG Timer Register (OTGTmr - 0x5000 C114)”), the TMR bit is set in
OTGIntSt, and the timer will be disabled.
2. Free running mode: an interrupt is generated at the end of TIMEOUT_CNT (see
Section 13.8.7 “
OTG Timer Register (OTGTmr - 0x5000 C114)”), the TMR bit is set,
and the timer value is reloaded into the counter. The timer is not disabled in this
mode.
Table 259. OTG Status Control register (OTGStCtrl - address 0x5000 C110) bit
description
Bit Symbol Description Reset
Value
1:0 PORT_FUNC Controls port function. Bit 0 is set or cleared by hardware
when B_HNP_TRACK or A_HNP_TRACK is set and
HNP succeeds. See Section 13.9
. Bit 1 is reserved.
-
3:2 TMR_SCALE Timer scale selection. This field determines the duration
of each timer count.
00: 10
s (100 KHz)
01: 100
s (10 KHz)
10: 1000
s (1 KHz)
11: Reserved
0x0
4 TMR_MODE Timer mode selection.
0: monoshot
1: free running
0
5 TMR_EN Timer enable. When set, TMR_CNT increments. When
cleared, TMR_CNT is reset to 0.
0
6 TMR_RST Timer reset. Writing one to this bit resets TMR_CNT to 0.
This provides a single bit control for the software to
restart the timer when the timer is enabled.
0
7 - Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
NA