UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 342 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
RS485/EIA-485 output inversion
The polarity of the direction control signal on the RTS
(or DTR) pins can be reversed by
programming bit 5 in the U1RS485CTRL register. When this bit is set, the direction control
pin will be driven to logic 1 when the transmitter has data waiting to be sent. The direction
control pin will be driven to logic 0 after the last bit of data has been transmitted.
15.5 Architecture
The architecture of the UART1 is shown below in the block diagram.
The APB interface provides a communications link between the CPU or host and the
UART1.
The UART1 receiver block, U1RX, monitors the serial input line, RXD1, for valid input.
The UART1 RX Shift Register (U1RSR) accepts valid characters via RXD1. After a valid
character is assembled in the U1RSR, it is passed to the UART1 RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
The UART1 transmitter block, U1TX, accepts data written by the CPU or host and buffers
the data in the UART1 TX Holding Register FIFO (U1THR). The UART1 TX Shift Register
(U1TSR) reads the data stored in the U1THR and assembles the data to transmit via the
serial output pin, TXD1.
The UART1 Baud Rate Generator block, U1BRG, generates the timing enables used by
the UART1 TX block. The U1BRG clock input source is the APB clock (PCLK). The main
clock is divided down per the divisor specified in the U1DLL and U1DLM registers. This
divided down clock is the 16x oversample clock.
The modem interface contains registers U1MCR and U1MSR. This interface is
responsible for handshaking between a modem peripheral and the UART1.
The interrupt interface contains registers U1IER and U1IIR. The interrupt interface
receives several one clock wide enables from the U1TX and U1RX blocks.
Status information from the U1TX and U1RX is stored in the U1LSR. Control information
for the U1TX and U1RX is stored in the U1LCR.
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