UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 142 of 841
10.1 Basic configuration
The Ethernet controller is configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bit PCENET.
Remark: On reset, the Ethernet block is disabled (PCENET = 0).
2. Clock: see Table 38
.
3. Pins: Enable Ethernet pins through the PINSEL registers and select their modes
through the PINMODE registers, see Section 8.5
.
4. Wake-up: Activity on the Ethernet port can wake up the microcontroller from
Power-down mode, see Section 4.8.8
.
5. Interrupts: Interrupts are enabled in the NVIC using the appropriate Interrupt Set
Enable register.
6. Initialization: see Section 10.17.2
.
10.2 Introduction
The Ethernet block contains a full featured 10 Mbps or 100 Mbps Ethernet MAC (Media
Access Controller) designed to provide optimized performance through the use of DMA
hardware acceleration. Features include a generous suite of control registers, half or full
duplex operation, flow control, control frames, hardware acceleration for transmit retry,
receive packet filtering and wake-up on LAN activity. Automatic frame transmission and
reception with Scatter-Gather DMA off-loads many operations from the CPU.
The Ethernet block is an AHB master that drives the AHB bus matrix. Through the matrix,
it has access to all on-chip RAM memories. A recommended use of RAM by the Ethernet
is to use one of the RAM blocks exclusively for Ethernet traffic. That RAM would then be
accessed only by the Ethernet and the CPU, and possibly the GPDMA, giving maximum
bandwidth to the Ethernet function.
The Ethernet block interfaces between an off-chip Ethernet PHY using the RMII (Reduced
Media Independent Interface) protocol and the on-chip MIIM (Media Independent
Interface Management) serial bus, also referred to as MDIO (Management Data
Input/Output).
UM10360
Chapter 10: LPC176x/5x Ethernet
Rev. 3 — 19 December 2013 User manual
Table 124. Ethernet acronyms, abbreviations, and definitions
Acronym or
Abbreviation
Definition
AHB Advanced High-performance bus
CRC Cyclic Redundancy Check
DMA Direct Memory Access
Double-word 64-bit entity
FCS Frame Check Sequence (CRC)
Fragment A (part of an) Ethernet frame; one or multiple fragments can add up to a single
Ethernet frame.
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