NXP Semiconductors LPC1768 - DMA Channel Source Address Registers (Dmaccxsrcaddr - 0 X5000 41 X0); DMA Channel Destination Address Registers (Dmaccxdestaddr - 0 X5000 41 X4); DMA Channel Linked List Item Registers (Dmaccxlli - 0 X5000 41 X8)

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User manual Rev. 3 — 19 December 2013 602 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.5.17 DMA Channel Source Address registers (DMACCxSrcAddr -
0x5000 41x0)
The eight read/write DMACCxSrcAddr Registers (DMACC0SrcAddr to DMACC7SrcAddr)
contain the current source address (byte-aligned) of the data to be transferred. Each
register is programmed directly by software before the appropriate channel is enabled.
When the DMA channel is enabled this register is updated:
• As the source address is incremented.
• By following the linked list when a complete packet of data has been transferred.
Reading the register when the channel is active does not provide useful information. This
is because by the time software has processed the value read, the address may have
progressed. It is intended to be read-only when the channel has stopped, in which case it
shows the source address of the last item read.
Note: The source and destination addresses must be aligned to the source and
destination widths.
Table 560
shows the bit assignments of the DMACCxSrcAddr Registers.
31.5.18 DMA Channel Destination Address registers (DMACCxDestAddr -
0x5000 41x4)
The eight read/write DMACCxDestAddr Registers (DMACC0DestAddr to
DMACC7DestAddr) contain the current destination address (byte-aligned) of the data to
be transferred. Each register is programmed directly by software before the channel is
enabled. When the DMA channel is enabled the register is updated as the destination
address is incremented and by following the linked list when a complete packet of data
has been transferred. Reading the register when the channel is active does not provide
useful information. This is because by the time that software has processed the value
read, the address may have progressed. It is intended to be read-only when a channel
has stopped, in which case it shows the destination address of the last item read.
Table 561
shows the bit assignments of the DMACCxDestAddr Register.
31.5.19 DMA Channel Linked List Item registers (DMACCxLLI - 0x5000 41x8)
The eight read/write DMACCxLLI Registers (DMACC0LLI to DMACC7LLI) contain a
word-aligned address of the next Linked List Item (LLI). If the LLI is 0, then the current LLI
is the last in the chain, and the DMA channel is disabled when all DMA transfers
associated with it are completed. Programming this register when the DMA channel is
enabled may have unpredictable side effects. Table 562
shows the bit assignments of the
DMACCxLLI Register.
Table 560. DMA Channel Source Address registers (DMACCxSrcAddr - 0x5000 41x0)
Bit Name Function
31:0 SrcAddr DMA source address. Reading this register will return the current source address.
Table 561. DMA Channel Destination Address registers (DMACCxDestAddr - 0x5000 41x4)
Bit Name Function
31:0 DestAddr DMA Destination address. Reading this register will return the current destination
address.