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User manual Rev. 3 — 19 December 2013 483 of 841
NXP Semiconductors
UM10360
Chapter 20: LPC176x/5x I2S
20.5.14 Receive Mode Control register (I2SRXMODE - 0x400A 8034)
The Receive Mode Control register contains additional controls for receive clock source,
enabling the 4-pin mode, and how MCLK is used. See Section 20.7
for a summary of
useful mode combinations.
Table 417: Transmit Mode Control register (I2STXMODE - 0x400A 8030) bit description
Bit Symbol Value Description Reset
Value
1:0 TXCLKSEL Clock source selection for the transmit bit clock divider. 0
00 Select the TX fractional rate divider clock output as the source
01 Reserved
10 Select the RX_MCLK signal as the TX_MCLK clock source
11 Reserved
2 TX4PIN Transmit 4-pin mode selection. When 1, enables 4-pin mode. 0
3 TXMCENA Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1,
output of TX_MCLK is enabled.
0
31:4 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 418: Receive Mode Control register (I2SRXMODE - 0x400A 8034) bit description
Bit Symbol Value Description Reset
Value
1:0 RXCLKSEL Clock source selection for the receive bit clock divider. 0
00 Select the RX fractional rate divider clock output as the source
01 Reserved
10 Select the TX_MCLK signal as the RX_MCLK clock source
11 Reserved
2 RX4PIN Receive 4-pin mode selection. When 1, enables 4-pin mode. 0
3 RXMCENA Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1,
output of RX_MCLK is enabled.
0
31:4 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
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