NXP Semiconductors LPC1768 - Control Logic and Register Bank; DMA Request and Response Interface; Channel Logic and Channel Register Bank; Interrupt Request

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 589 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.4.1.2 Control logic and register bank
The register block stores data written or to be read across the AHB interface.
31.4.1.3 DMA request and response interface
See Section 31.4.2 for information on the DMA request and response interface.
31.4.1.4 Channel logic and channel register bank
The channel logic and channel register bank contains registers and logic required for each
DMA channel.
31.4.1.5 Interrupt request
The interrupt request generates the interrupt to the ARM processor.
31.4.1.6 AHB master interface
The DMA Controller contains one AHB master interface. The AHB master is capable of
dealing with all types of AHB transactions, including:
• Split, retry, and error responses from slaves. If a peripheral performs a split or retry,
the DMA Controller stalls and waits until the transaction can complete.
• Locked transfers for source and destination of each stream.
• Setting of protection bits for transfers on each stream.
31.4.1.6.1 Bus and transfer widths
The physical width of the AHB bus is 32 bits. Source and destination transfers can be of
differing widths and can be the same width or narrower than the physical bus width. The
DMA Controller packs or unpacks data as appropriate.
31.4.1.6.2 Endian behavior
The DMA Controller can cope with both little-endian and big-endian addressing.
Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32-bit data
bus is observed.
Note: If byte swapping is not required, then use of different endianness between the
source and destination addresses must be avoided. Table 542
shows endian behavior for
different source and destination combinations.