UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 373 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
16.9.1 Central Transmit Status Register (CANTxSR - 0x4004 0000)
16.9.2 Central Receive Status Register (CANRxSR - 0x4004 0004)
Table 337. Central Transit Status Register (CANTxSR - address 0x4004 0000) bit description
Bit Symbol Description Reset Value
0 TS1 When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR). 0
1 TS2 When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR) 0
7:2 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
8 TBS1 When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in
CAN1GSR).
1
9 TBS2 When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in
CAN2GSR).
1
15:10 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
16 TCS1 When 1, all requested transmissions have been completed successfully by the CAN1
controller (same as TCS in CAN1GSR).
1
17:16 TCS2 When 1, all requested transmissions have been completed successfully by the CAN2
controller (same as TCS in CAN2GSR).
1
31:18 - Reserved, the value read from a reserved bit is not defined. NA
Table 338. Central Receive Status Register (CANRxSR - address 0x4004 0004) bit description
Bit Symbol Description Reset Value
0 RS1 When 1, CAN1 is receiving a message (same as RS in CAN1GSR). 0
1 RS2 When 1, CAN2 is receiving a message (same as RS in CAN2GSR). 0
7:2 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
8 RB1 When 1, a received message is available in the CAN1 controller (same as RBS in
CAN1GSR).
0
9 RB2 When 1, a received message is available in the CAN2 controller (same as RBS in
CAN2GSR).
0
15:10 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
16 DOS1 When 1, a message was lost because the preceding message to CAN1 controller was not
read out quickly enough (same as DOS in CAN1GSR).
0
17:16 DOS2 When 1, a message was lost because the preceding message to CAN2 controller was not
read out quickly enough (same as DOS in CAN2GSR).
0
31:18 - Reserved, the value read from a reserved bit is not defined. NA
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