NXP Semiconductors LPC1768 - Baud Rate Prescaler; Synchronization Jump Width; Time Segment 1 and Time Segment 2; CAN Error Warning Limit Register (CAN1 EWL - 0 X4004 4018, CAN2 EWL - 0 X4004 8018)

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User manual Rev. 3 — 19 December 2013 363 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
Baud rate prescaler
The period of the CAN system clock t
SCL
is programmable and determines the individual
bit timing. The CAN system clock t
SCL
is calculated using the following equation:
(7)
Synchronization jump width
To compensate for phase shifts between clock oscillators of different bus controllers, any
bus controller must re-synchronize on any relevant signal edge of the current
transmission. The synchronization jump width t
SJW
defines the maximum number of clock
cycles a certain bit period may be shortened or lengthened by one re-synchronization:
(8)
Time segment 1 and time segment 2
Time segments TSEG1 and TSEG2 determine the number of clock cycles per bit period
and the location of the sample point:
(9)
(10)
(11)
16.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018,
CAN2EWL - 0x4004 8018)
This register sets a limit on Tx or Rx errors at which an interrupt can occur. It can be read
at any time but can only be written if the RM bit in CANmod is 1.
23 SAM Sampling
0 The bus is sampled once (recommended for high speed buses) 0 X
1 The bus is sampled 3 times (recommended for low to medium speed buses to filter
spikes on the bus-line)
31:24 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit
description …continued
Bit Symbol Value Function Reset
Value
RM
Set
t
SCL
t
CANsuppliedCLK
BRP 1+=
t
SJW
t
SCL
SJW 1+=
t
SYNCSEG
t
SCL
=
t
TSEG1
t
SCL
TSEG1 1+=
t
TSEG2
t
SCL
TSEG2 1+=
Table 323. CAN Error Warning Limit register (CAN1EWL - address 0x4004 4018, CAN2EWL - address 0x4004 8018)
bit description
Bit Symbol Function Reset
Value
RM
Set
7:0 EWL During CAN operation, this value is compared to both the Tx and Rx Error Counters. If
either of these counter matches this value, the Error Status (ES) bit in CANSR is set.
9610 = 0x6
0
X
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA