UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 771 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
[1] This is the same value as IPSR bits[8:0], see Table 629 “IPSR bit assignments”.
When you write to the ICSR, the effect is unpredictable if you:
• write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit
• write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.
34.4.3.5 Vector Table Offset Register
The VTOR indicates the offset of the vector table base address from memory address
0x00000000
. See the register summary in Table 654 for its attributes.
The bit assignments are shown in Table 658
.
[25] PENDSTCLR WO SysTick exception clear-pending bit.
Write:
0 = no effect
1 = removes the pending state from the SysTick exception.
This bit is WO. On a register read its value is Unknown.
[24] - - Reserved.
[23] Reserved for
Debug use
RO This bit is reserved for Debug use and reads-as-zero when
the processor is not in Debug.
[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:
0 = interrupt not pending
1 = interrupt pending.
[21:18] - - Reserved.
[17:12] VECTPENDING RO Indicates the exception number of the highest priority pending
enabled exception:
0 = no pending exceptions
Nonzero = the exception number of the highest priority
pending enabled exception.
The value indicated by this field includes the effect of the
BASEPRI and FAULTMASK registers, but not any effect of the
PRIMASK register.
[11] RETTOBASE RO Indicates whether there are preempted active exceptions:
0 = there are preempted active exceptions to execute
1 = there are no active exceptions, or the currently-executing
exception is the only active exception.
[10:9] - - Reserved.
[8:0] VECTACTIVE
[1]
RO Contains the active exception number:
0 = Thread mode
Nonzero = The exception number
[1]
of the currently active
exception.
Remark: Subtract 16 from this value to obtain the IRQ
number required to index into the Interrupt Clear-Enable,
Set-Enable, Clear-Pending, Set-Pending, or Priority
Registers, see Table 629 “
IPSR bit assignments”.
Table 657. ICSR bit assignments …continued
Bits Name Type Function
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