UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 733 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
Execution Program Status Register: The EPSR contains the Thumb state bit, and the
execution state bits for either the:
• If-Then (IT) instruction
• Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or
store multiple instruction.
See the register summary in Table 626
for the EPSR attributes. The bit assignments are:
Attempts to read the EPSR directly through application software using the
MSR
instruction
always return zero. Attempts to write the EPSR using the
MSR
instruction in application
software are ignored. Fault handlers can examine EPSR value in the stacked PSR to
indicate the operation that is at fault. See Section 34.3.3.7
Table 629. IPSR bit assignments
Bits Name Function
[31:9] - Reserved
[8:0] ISR_NUMBER This is the number of the current exception:
0 = Thread mode
1 = Reserved
2 = NMI
3 = Hard fault
4 = Memory management fault
5 = Bus fault
6 = Usage fault
7-10 = Reserved
11 = SVCall
12 = Reserved for Debug
13 = Reserved
14 = PendSV
15 = SysTick
16 = IRQ0
17 = IRQ1, first device specific interrupt
.
.
255 = IRQ243 (last implemented interrupt depends on device)
see Section 34.3.3.2
for more information.
Table 630. EPSR bit assignments
Bits Name Function
[31:27] - Reserved.
[26:25], [15:10] ICI Interruptible-continuable instruction bits, see Section
.
[26:25], [15:10] IT Indicates the execution state bits of the
IT
instruction, see
Section 34.2.9.3 “
IT”.
[24] T Always set to 1.
[23:16] - Reserved.
[9:0] - Reserved.
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