UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 362 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
16.7.6 CAN Bus Timing Register (CAN1BTR - 0x4004 4014, CAN2BTR -
0x4004 8014)
This register controls how various CAN timings are derived from the APB clock. It defines
the values of the Baud Rate Prescaler (BRP) and the Synchronization Jump Width (SJW).
Furthermore, it defines the length of the bit period, the location of the sample point and the
number of samples to be taken at each sample point. It can be read at any time but can
only be written if the RM bit in CANmod is 1.
4 WUIE Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt
is requested.
0X
5 EPIE Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error
active to error passive or vice versa, the respective interrupt is requested.
0X
6 ALIE Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective
interrupt is requested.
0X
7 BEIE Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the
respective interrupt.
0X
8 IDIE ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller
requests the respective interrupt.
0X
9 TIE2 Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted
out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission
command), the CAN Controller requests the respective interrupt.
0X
10 TIE3 Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted
out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission
command), the CAN Controller requests the respective interrupt.
0X
31:11 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 321. CAN Interrupt Enable Register (CAN1IER - address 0x4004 4010, CAN2IER - address 0x4004 8010) bit
description …continued
Bit Symbol Function Reset
Value
RM
Set
Table 322. CAN Bus Timing Register (CAN1BTR - address 0x4004 4014, CAN2BTR - address 0x4004 8014) bit
description
Bit Symbol Value Function Reset
Value
RM
Set
9:0 BRP Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the
CAN clock.
0X
13:10 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
15:14 SJW The Synchronization Jump Width is (this value plus one) CAN clocks. 0 X
19:16 TESG1 The delay from the nominal Sync point to the sample point is (this value plus one)
CAN clocks.
1100 X
22:20 TESG2 The delay from the sample point to the next nominal sync point is (this value plus one)
CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3)
CAN clocks.
001 X
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