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NXP Semiconductors LPC1768 - Uartn Scratch Pad Register (U0 SCR - 0 X4000 C01 C, U2 SCR - 0 X4009 801 C U3 SCR - 0 X4009 C01 C); Uartn Auto-Baud Control Register (U0 ACR - 14.5 0 X4000 C020, U2 ACR - 0 X4009 8020, U3 ACR - 0 X4009 C020)

NXP Semiconductors LPC1768
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UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 309 of 841
NXP Semiconductors
UM10360
Chapter 14: LPC176x/5x UART0/2/3
14.4.9 UARTn Scratch Pad Register (U0SCR - 0x4000 C01C, U2SCR -
0x4009 801C U3SCR - 0x4009 C01C)
The UnSCR has no effect on the UARTn operation. This register can be written and/or
read at user’s discretion. There is no provision in the interrupt interface that would indicate
to the host that a read or write of the UnSCR has occurred.
14.4.10 UARTn Auto-baud Control Register (U0ACR - 0x4000 C020, U2ACR -
0x4009 8020, U3ACR - 0x4009 C020)
The UARTn Auto-baud Control Register (UnACR) controls the process of measuring the
incoming clock/data rate for the baud rate generation and can be read and written at
user’s discretion.
7 Error in RX FIFO
(RXFE)
UnLSR[7] is set when a character with a Rx error such as framing error, parity
error or break interrupt, is loaded into the UnRBR. This bit is cleared when the
UnLSR register is read and there are no subsequent errors in the UARTn FIFO.
0
0 UnRBR contains no UARTn RX errors or UnFCR[0]=0.
1 UARTn RBR contains at least one UARTn RX error.
31:8 - Reserved, the value read from a reserved bit is not defined. NA
Table 280: UARTn Line Status Register (U0LSR - address 0x4000 C014, U2LSR - 0x4009 8014, U3LSR - 0x4009 C014)
bit description …continued
Bit Symbol Value Description Reset
Value
Table 281: UARTn Scratch Pad Register (U0SCR - address 0x4000 C01C, U2SCR - 0x4009 801C, U3SCR -
0x4009 C01C) bit description
Bit Symbol Description Reset Value
7:0 Pad A readable, writable byte. 0x00
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 282: UARTn Auto-baud Control Register (U0ACR - address 0x4000 C020, U2ACR - 0x4009 8020, U3ACR -
0x4009 C020) bit description
Bit Symbol Value Description Reset value
0 Start This bit is automatically cleared after auto-baud completion. 0
0 Auto-baud stop (auto-baud is not running).
1 Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is
automatically cleared after auto-baud completion.
1 Mode Auto-baud mode select bit. 0
0 Mode 0.
1 Mode 1.
2 AutoRestart 0 No restart. 0
1 Restart in case of time-out (counter restarts at next UARTn Rx falling edge) 0
7:3 - Reserved, user software should not write ones to reserved bits. The value
read from a reserved bit is not defined.
NA

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