NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 666 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.4.3 LDR and STR, register offset
Load and Store with register offset.
34.2.4.3.1 Syntax
op{type}{cond} Rt, [Rn, Rm {, LSL #n}]
where:
op is one of:
LDR : Load Register.
STR : Store Register.
type is one of:
B : unsigned byte, zero extend to 32 bits on loads.
SB : signed byte, sign extend to 32 bits ( LDR only).
H : unsigned halfword, zero extend to 32 bits on loads.
SH : signed halfword, sign extend to 32 bits ( LDR only).
—: omit, for word.
cond is an optional condition code, see Section 34.2.3.7 “
Conditional execution”.
Rt is the register to load or store.
Rn is the register on which the memory address is based.
Rm is a register containing a value to be used as the offset.
LSL #n is an optional shift, with n in the range 0 to 3.
34.2.4.3.2 Operation
LDR instructions load a register with a value from memory.
STR instructions store a register value into memory.
The memory address to load from or store to is at an offset from the register Rn. The
offset is specified by the register Rm and can be shifted left by up to 3 bits using
LSL .
The value to load or store can be a byte, halfword, or word. For load instructions, bytes
and halfwords can either be signed or unsigned. See Section 34.2.3.5 “
Address
alignment”.
34.2.4.3.3 Restrictions
In these instructions:
• Rn must not be PC
• Rm must not be SP and must not be PC
• Rt can be SP only for word loads and word stores
• Rt can be PC only for word loads.
When Rt is PC in a word load instruction:

NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English