UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 730 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
[1] Describes access type during program execution in thread mode and Handler mode. Debug access can differ.
[2] An entry of Either means privileged and unprivileged software can access the register.
34.3.1.3.1 General-purpose registers
R0-R12 are 32-bit general-purpose registers for data operations.
34.3.1.3.2 Stack Pointer
The Stack Pointer (SP) is register R13. In Thread mode, bit[1] of the CONTROL register
indicates the stack pointer to use:
On reset, the processor loads the MSP with the value from address
0x00000000
.
• 0 = Main Stack Pointer (MSP). This is the reset value.
• 1 = Process Stack Pointer (PSP).
34.3.1.3.3 Link Register
The Link Register (LR) is register R14. It stores the return information for subroutines,
function calls, and exceptions. On reset, the processor loads the LR value
0xFFFFFFFF.
34.3.1.3.4 Program Counter
The Program Counter (PC) is register R15. It contains the current program address.
Bit[0] is always 0 because instruction fetches must be halfword aligned. On reset, the
processor loads the PC with the value of the reset vector, which is at address
0x00000004
.
34.3.1.3.5 Program Status Register
The Program Status Register (PSR) combines:
• Application Program Status Register (APSR)
• Interrupt Program Status Register (IPSR)
• Execution Program Status Register (EPSR).
These registers are mutually exclusive bitfields in the 32-bit PSR. The bit assignments
are:
EPSR RO Privileged
0x01000000
Table 630
PRIMASK RW Privileged
0x00000000
Table 631
FAULTMASK RW Privileged
0x00000000
Table 632
BASEPRI RW Privileged
0x00000000
Table 633
CONTROL RW Privileged
0x00000000
Table 634
Table 626. Core register set summary …continued
Name Type
[1]
Required
privilege
[2]
Reset
value
Description
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