NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 655 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
The permitted shift lengths depend on the shift type and the instruction, see the individual
instruction description or Section 34.2.3.3
. If the shift length is 0, no shift occurs. Register
shift operations update the carry flag except when the specified shift length is 0. The
following sub-sections describe the various shift operations and how they affect the carry
flag. In these descriptions, Rm is the register containing the value to be shifted, and n is
the shift length.
34.2.3.4.1 ASR
Arithmetic shift right by n bits moves the left-hand
32 -n bits of the register Rm, to the right
by n places, into the right-hand
32 -n bits of the result. And it copies the original bit[31] of
the register into the left-hand n bits of the result. See Figure 141
.
You can use the ASR #n operation to divide the value in the register Rm by 2
n
, with the
result being rounded towards negative-infinity.
When the instruction is
ASRS or when ASR #n is used in Operand2 with the instructions
MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST , the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Note
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm.
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm.
34.2.3.4.2 LSR
Logical shift right by n bits moves the left-hand
32 -n bits of the register Rm, to the right by
n places, into the right-hand
32 -n bits of the result. And it sets the left-hand n bits of the
result to 0. See Figure 142
.
You can use the LSR #n operation to divide the value in the register Rm by 2
n
, if the value
is regarded as an unsigned integer.
When the instruction is
LSRS or when LSR #n is used in Operand2 with the instructions
MOVS , MVNS , ANDS , ORRS , ORNS , EORS , BICS , TEQ or TST , the carry flag is updated to the last bit
shifted out, bit[n-1], of the register Rm.
Note
• If n is 32 or more, then all the bits in the result are cleared to 0.
Fig 141. ASR #3
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NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English