UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 260 of 841
NXP Semiconductors
UM10360
Chapter 11: LPC176x/5x USB device controller
11.15.4.10 Packet_valid
This bit is used for isochronous endpoints. It indicates whether the last packet transferred
to the memory is received with errors or not. This bit is set if the packet is valid, i.e., it was
received without errors. See Section 11.15.6 “
Isochronous endpoint operation” on page
262 for isochronous endpoint operation.
This bit is unnecessary for non-isochronous endpoints because a DMA request is
generated only for packets without errors, and thus Packet_valid will always be set when
the request is generated.
11.15.4.11 LS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Least Significant Byte (LSB) of
the transfer length has been extracted. The extracted size is reflected in the
DMA_buffer_length field, bits 23:16.
11.15.4.12 MS_byte_extracted
Used in ATLE mode. When set, this bit indicates that the Most Significant Byte (MSB) of
the transfer size has been extracted. The size extracted is reflected in the
DMA_buffer_length field, bits 31:24. Extraction stops when LS_Byte_extracted and
MS_byte_extracted bits are set.
11.15.4.13 Present_DMA_count
The number of bytes transferred by the DMA engine. The DMA engine updates this field
after completing each packet transfer.
For isochronous endpoints, Present_DMA_count is the number of packets transferred; for
non-isochronous endpoints, Present_DMA_count is the number of bytes.
11.15.4.14 Message_length_position
Used in ATLE mode. This field gives the offset of the message length position embedded
in the incoming data packets. This is applicable only for OUT endpoints. Offset 0 indicates
that the message length starts from the first byte of the first packet.
11.15.4.15 Isochronous_packetsize_memory_address
The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See Figure 31
. This is applicable to isochronous
endpoints only.
11.15.5 Non-isochronous endpoint operation
11.15.5.1 Setting up DMA transfers
Software prepares the DMA Descriptors (DDs) for those physical endpoints to be enabled
for DMA transfer. These DDs are present in on-chip RAM. The start address of the first
DD is programmed into the DMA Description pointer (DDP) location for the corresponding
endpoint in the UDCA. Software then sets the EPxx_DMA_ENABLE bit for this endpoint in
the USBEpDMAEn register (Section 11.10.7.6
).The DMA_mode bit field in the descriptor
is set to ‘00’ for normal mode operation. All other DD fields are initialized as specified in
Table 251
.
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