UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 593 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
DMACTC[15:0] — DMA terminal count signals. The DMACTC signal can be used by the
DMA controller to indicate to the peripheral that the DMA transfer is complete.
31.4.2.3 DMA request connections
The connection of the GPDMA to the supported peripheral devices depends on the DMA
functions implemented in those peripherals. Table 543
shows the DMA Request numbers
used by the supported peripherals. UART and timer DMA requests on channels 8 through
15 are chosen via the DMAREQSEL register, see Section 31.5.15
.
[1] Generates an interrupt and/or DMA request depending on software setup.
Table 543. DMA Connections
Peripheral Function DMA Single Request
Input (DMACSREQ)
DMA Burst Request
Input (DMACBREQ)
DMA Request Signal
SSP0 Tx 0 0 Dedicated DMA requests
SSP0 Rx 1 1 Dedicated DMA requests
SSP1 Tx 2 2 Dedicated DMA requests
SSP1 Rx 3 3 Dedicated DMA requests
ADC 4 4 ADC interrupt request
[1]
I
2
S channel 0 - 5 Dedicated DMA request
I
2
S channel 1 - 6 Dedicated DMA request
DAC - 7 Dedicated DMA request
UART0 Tx / MAT0.0 - 8 Dedicated DMA requests
UART0 Rx / MAT0.1 - 9 Dedicated DMA requests
UART1 Tx / MAT1.0 - 10 Dedicated DMA requests
UART1 Rx / MAT1.1 - 11 Dedicated DMA requests
UART2 Tx / MAT2.0 - 12 Dedicated DMA requests
UART2 Rx / MAT2.1 - 13 Dedicated DMA requests
UART3 Tx / MAT3.0 - 14 Dedicated DMA requests
UART3 Rx / MAT3.1 - 15 Dedicated DMA requests
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