UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 340 of 841
NXP Semiconductors
UM10360
Chapter 15: LPC176x/5x UART1
15.4.19 UART1 RS-485 Address Match register (U1RS485ADRMATCH -
0x4001 0050)
The U1RS485ADRMATCH register contains the address match value for RS-485/EIA-485
mode.
15.4.20 UART1 RS-485 Delay value register (U1RS485DLY - 0x4001 0054)
The user may program the 8-bit RS485DLY register with a delay between the last stop bit
leaving the TXFIFO and the de-assertion of RTS
(or DTR). This delay time is in periods of
the baud clock. Any delay time from 0 to 255 bit times may be programmed.
15.4.21 RS-485/EIA-485 modes of operation
The RS-485/EIA-485 feature allows the UART to be configured as an addressable slave.
The addressable slave is one of multiple slaves controlled by a single master.
The UART master transmitter will identify an address character by setting the parity (9th)
bit to ‘1’. For data characters, the parity bit is set to ‘0’.
Each UART slave receiver can be assigned a unique address. The slave can be
programmed to either manually or automatically reject data following an address which is
not theirs.
RS-485/EIA-485 Normal Multidrop Mode (NMM)
Setting the RS485CTRL bit 0 enables this mode. In this mode, an address is detected
when a received byte causes the UART to set the parity error and generate an interrupt.
5 OINV This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin. 0
0 The direction control pin will be driven to logic ‘0’ when the transmitter has data to
be sent. It will be driven to logic ‘1’ after the last bit of data has been transmitted.
1 The direction control pin will be driven to logic ‘1’ when the transmitter has data to
be sent. It will be driven to logic ‘0’ after the last bit of data has been transmitted.
31:6 - - Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
Table 308: UART1 RS485 Control register (U1RS485CTRL - address 0x4001 004C) bit description
Bit Symbol Value Description Reset value
Table 309. UART1 RS-485 Address Match register (U1RS485ADRMATCH - address 0x4001 0050) bit description
Bit Symbol Description Reset value
7:0 ADRMATCH Contains the address match value. 0x00
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 310. UART1 RS-485 Delay value register (U1RS485DLY - address 0x4001 0054) bit description
Bit Symbol Description Reset value
7:0 DLY Contains the direction control (RTS or DTR) delay value. This register works in
conjunction with an 8-bit counter.
0x00
31:8 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
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