NXP Semiconductors LPC1768 - Memory Access Instructions

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 661 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.4 Memory access instructions
Table 616 shows the memory access instructions:
Table 616. Memory access instructions
Mnemonic Brief description See
ADR Load PC-relative address Section 34.2.4.1
CLREX Clear Exclusive Section 34.2.4.9
LDM{mode} Load Multiple registers Section 34.2.4.6
LDR{type} Load Register using immediate offset Section 34.2.4.2
LDR{type} Load Register using register offset Section 34.2.4.3
LDR{type}T Load Register with unprivileged access Section 34.2.4.4
LDR Load Register using PC-relative address Section 34.2.4.5
LDREX{type} Load Register Exclusive Section 34.2.4.8
POP Pop registers from stack Section 34.2.4.7
PUSH Push registers onto stack Section 34.2.4.7
STM{mode} Store Multiple registers Section 34.2.4.6
STR{type} Store Register using immediate offset Section 34.2.4.2
STR{type} Store Register using register offset Section 34.2.4.3
STR{type}T Store Register with unprivileged access Section 34.2.4.4
STREX{type} Store Register Exclusive Section 34.2.4.8