NXP Semiconductors LPC1768 User Manual

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 444 of 841
NXP Semiconductors
UM10360
Chapter 19: LPC176x/5x I2C0/1/2
AAC is the Assert Acknowledge Clear bit. Writing a 1 to this bit clears the AA bit in the
I2CONSET register. Writing 0 has no effect.
SIC is the I
2
C Interrupt Clear bit. Writing a 1 to this bit clears the SI bit in the I2CONSET
register. Writing 0 has no effect.
STAC is the START flag Clear bit. Writing a 1 to this bit clears the STA bit in the
I2CONSET register. Writing 0 has no effect.
I2ENC is the I
2
C Interface Disable bit. Writing a 1 to this bit clears the I2EN bit in the
I2CONSET register. Writing 0 has no effect.
19.8.3 I
2
C Status register (I2STAT: I
2
C0, I2C0STAT - 0x4001 C004; I
2
C1,
I2C1STAT - 0x4005 C004; I
2
C2, I2C2STAT - 0x400A 0004)
Each I
2
C Status register reflects the condition of the corresponding I
2
C interface. The I
2
C
Status register is read-only.
The three least significant bits are always 0. Taken as a byte, the status register contents
represent a status code. There are 26 possible status codes. When the status code is
0xF8, there is no relevant information available and the SI bit is not set. All other 25 status
codes correspond to defined I
2
C states. When any of these states entered, the SI bit will
be set. For a complete list of status codes, refer to tables from Table 398
to Table 401.
19.8.4 I
2
C Data register (I2DAT: I
2
C0, I2C0DAT - 0x4001 C008; I
2
C1, I2C1DAT -
0x4005 C008; I
2
C2, I2C2DAT - 0x400A 0008)
This register contains the data to be transmitted or the data just received. The CPU can
read and write to this register only while it is not in the process of shifting a byte, when the
SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is
always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a
byte has been received, the first bit of received data is located at the MSB of I2DAT.
4 - Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
5 STAC START flag Clear bit.
6I2ENCI
2
C interface Disable bit.
31:7 - Reserved. User software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
Table 385. I
2
C Control Clear register (I2CONCLR: I
2
C0, I2C0CONCLR - 0x4001 C018;
I
2
C1, I2C1CONCLR - 0x4005 C018; I
2
C2, I2C2CONCLR - 0x400A 0018) bit
description …continued
Bit Symbol Description
Table 386. I
2
C Status register (I2STAT: I
2
C0, I2C0STAT - 0x4001 C004; I
2
C1, I2C1STAT -
0x4005 C004; I
2
C2, I2C2STAT - 0x400A 0004) bit description
Bit Symbol Description Reset
value
2:0 - These bits are unused and are always 0. 0
7:3 Status These bits give the actual status information about the I
2
C interface. 0x1F
31:8 - Reserved. The value read from a reserved bit is not defined. NA

NXP Semiconductors LPC1768 Specifications

General

Brand	NXP Semiconductors
Model	LPC1768
Category	Microcontrollers
Language	English