UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 491 of 841
21.1 Basic configuration
The Timer 0, 1, 2, and 3 peripherals are configured using the following registers:
1. Power: In the PCONP register (Table 46
), set bits PCTIM0/1/2/3.
Remark: On reset, Timer0/1 are enabled (PCTIM0/1 = 1), and Timer2/3 are disabled
(PCTIM2/3 = 0).
2. Peripheral clock: In the PCLKSEL0 register (Table 40
), select PCLK_TIMER0/1; in the
PCLKSEL1 register (Table 41
), select PCLK_TIMER2/3.
3. Pins: Select timer pins through the PINSEL registers. Select the pin modes for the
port pins with timer functions through the PINMODE registers (Section 8.5
).
4. Interrupts: See register T0/1/2/3MCR (Table 429
) and T0/1/2/3CCR (Table 430) for
match and capture events. Interrupts are enabled in the NVIC using the appropriate
Interrupt Set Enable register.
5. DMA: Up to two match conditions can be used to generate timed DMA requests, see
Table 543
.
21.2 Features
Remark: The four Timer/Counters are identical except for the peripheral base address. A
minimum of two Capture inputs and two Match outputs are pinned out for all four timers,
with a choice of multiple pins for each. Timer 2 brings out all four Match outputs.
• A 32-bit Timer/Counter with a programmable 32-bit Prescaler.
• Counter or Timer operation
• Up to two 32-bit capture channels per timer, that can take a snapshot of the timer
value when an input signal transitions. A capture event may also optionally generate
an interrupt.
• Four 32-bit match registers that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set low on match.
– Set high on match.
– Toggle on match.
– Do nothing on match.
UM10360
Chapter 21: LPC176x/5x Timer 0/1/2/3
Rev. 3 — 19 December 2013 User manual