UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 579 of 841
NXP Semiconductors
UM10360
Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC)
29.5.2 A/D Global Data Register (AD0GDR - 0x4003 4004)
The A/D Global Data Register holds the result of the most recent A/D conversion that has
completed, and also includes copies of the status flags that go with that conversion.
Results of ADC conversion can be read in one of two ways. One is to use the A/D Global
Data Register to read all data from the ADC. Another is to use the
A/D Channel Data
Registers
. It is important to use one method consistently because the DONE and
OVERRUN flags can otherwise get out of synch between the AD0GDR and the
A/D
Channel Data Register
s, potentially causing erroneous interrupts or DMA activity.
29.5.3 A/D Interrupt Enable register (AD0INTEN - 0x4003 400C)
This register allows control over which A/D channels generate an interrupt when a
conversion is complete. For example, it may be desirable to use some A/D channels to
monitor sensors by continuously performing conversions on them. The most recent
results are read by the application program whenever they are needed. In this case, an
interrupt is not desirable at the end of each conversion for some A/D channels.
Table 532: A/D Global Data Register (AD0GDR - address 0x4003 4004) bit description
Bit Symbol Description Reset
value
3:0 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
15:4 RESULT When DONE is 1, this field contains a binary fraction representing the voltage on
the AD0[n] pin selected by the SEL field, as it falls within the range of V
REFP
to
V
REFN
. Zero in the field indicates that the voltage on the input pin was less than,
equal to, or close to that on V
REFN
, while 0xFFF indicates that the voltage on the
input was close to, equal to, or greater than that on V
REFP
.
NA
23:16 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
26:24 CHN These bits contain the channel from which the RESULT bits were converted (e.g.
000 identifies channel 0, 001 channel 1...).
NA
29:27 - Reserved, user software should not write ones to reserved bits. The value read from
a reserved bit is not defined.
NA
30 OVERRUN This bit is 1 in burst mode if the results of one or more conversions was (were) lost
and overwritten before the conversion that produced the result in the RESULT bits.
This bit is cleared by reading this register.
0
31 DONE This bit is set to 1 when an A/D conversion completes. It is cleared when this
register is read and when the ADCR is written. If the ADCR is written while a
conversion is still in progress, this bit is set and a new conversion is started.
0
Table 533: A/D Interrupt Enable register (AD0INTEN - address 0x4003 400C) bit description
Bit Symbol Value Description Reset
value
0 ADINTEN0 0 Completion of a conversion on ADC channel 0 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 0 will generate an interrupt.
1 ADINTEN1 0 Completion of a conversion on ADC channel 1 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 1 will generate an interrupt.
2 ADINTEN2 0 Completion of a conversion on ADC channel 2 will not generate an interrupt. 0
1 Completion of a conversion on ADC channel 2 will generate an interrupt.
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