UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 582 of 841
NXP Semiconductors
UM10360
Chapter 29: LPC176x/5x Analog-to-Digital Converter (ADC)
29.6 Operation
Once an ADC conversion is started, it cannot be interrupted. A new software write to
launch a new conversion or a new edge-trigger event will be ignored while the previous
conversion is in progress.
29.6.1 Hardware-triggered conversion
If the BURST bit in the ADCR is 0 and the START field contains 010-111, the ADC will
start a conversion when a transition occurs on a selected pin or Timer Match signal. The
choices include conversion on a specified edge of any of 4 Match signals, or conversion
on a specified edge of either of 2 Capture/Match pins. The pin state from the selected pad
or the selected Match signal, XORed with ADCR bit 27, is used in the edge detection
logic.
29.6.2 Interrupts
An interrupt request is asserted to the NVIC when the DONE bit is 1. Software can use the
Interrupt Enable bit for the A/D Converter in the NVIC to control whether this assertion
results in an interrupt. DONE is negated when the ADDR is read.
29.6.3 Accuracy vs. digital receiver
The ADC function must be selected via the PINSEL registers in order to get accurate
voltage readings on the monitored pin. The PINMODE should also be set to the mode for
which neither pull-up nor pull-down resistor is enabled. For a pin hosting an ADC input, it
is not possible to have a have a digital function selected and yet get valid ADC readings.
An inside circuit disconnects ADC hardware from the associated pin whenever a digital
function is selected on that pin.
29.6.4 DMA control
A DMA transfer request is generated from the ADC interrupt request line. To generate a
DMA transfer the same conditions must be met as the conditions for generating an
interrupt (see Section 29.6.2
and Section 29.5.3).
Remark: If the DMA is used, the ADC interrupt must be disabled in the NVIC.
For DMA transfers, only burst requests are supported. The burst size can be set to one in
the DMA channel control register (see Section 31.5.20
). If the number of ADC channels is
not equal to one of the other DMA-supported burst sizes (applicable DMA burst sizes are
1, 4, 8 - see Section 31.5.20
), set the burst size to one.
The DMA transfer size determines when a DMA interrupt is generated. The transfer size
can be set to the number of ADC channels being converted (see Section 31.5.20
).
Non-contiguous channels can be transferred by the DMA using the scatter/gather linked
lists (see Section 31.5.19
).
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