UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 728 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.3 ARM Cortex-M3 User Guide: Processor
34.3.1 Programmers model
This section describes the Cortex-M3 programmers model. In addition to the individual
core register descriptions, it contains information about the processor modes and privilege
levels for software execution and stacks.
34.3.1.1 Processor mode and privilege levels for software execution
The processor modes are:
• Thread mode
Used to execute application software. The processor enters Thread mode when it
comes out of reset.
• Handler mode
Used to handle exceptions. The processor returns to Thread mode when it has
finished exception processing.
The privilege levels for software execution are:
• Unprivileged
The software:
– has limited access to the
MSR
and
MRS
instructions, and cannot use the
CPS
instruction
– cannot access the system timer, NVIC, or system control block
– might have restricted access to memory or peripherals.
Unprivileged software executes at the unprivileged level.
• Privileged
The software can use all the instructions and has access to all resources.
Privileged software executes at the privileged level.
In Thread mode, the CONTROL register controls whether software execution is privileged
or unprivileged, see Table 634
. In Handler mode, software execution is always privileged.
Only privileged software can write to the CONTROL register to change the privilege level
for software execution in Thread mode. Unprivileged software can use the
SVC
instruction
to make a supervisor call to transfer control to privileged software.
34.3.1.2 Stacks
The processor uses a full descending stack. This means the stack pointer indicates the
last stacked item on the stack memory. When the processor pushes a new item onto the
stack, it decrements the stack pointer and then writes the item to the new memory
location. The processor implements two stacks, the main stack and the process stack,
with independent copies of the stack pointer, see Section 34.3.1.3.2
.
In Thread mode, the CONTROL register controls whether the processor uses the main
stack or the process stack, see Table 634
. In Handler mode, the processor always uses
the main stack. The options for processor operations are:
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