UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 307 of 841
NXP Semiconductors
UM10360
Chapter 14: LPC176x/5x UART0/2/3
UART transmitter DMA
In DMA mode, the transmitter DMA request is asserted on the event of the transmitter
FIFO transitioning to not full. The transmitter DMA request is cleared by the DMA
controller.
14.4.7 UARTn Line Control Register (U0LCR - 0x4000 C00C, U2LCR -
0x4009 800C, U3LCR - 0x4009 C00C)
The UnLCR determines the format of the data character that is to be transmitted or
received.
14.4.8 UARTn Line Status Register (U0LSR - 0x4000 C014, U2LSR -
0x4009 8014, U3LSR - 0x4009 C014)
The UnLSR is a read-only register that provides status information on the UARTn TX and
RX blocks.
Table 279: UARTn Line Control Register (U0LCR - address 0x4000 C00C, U2LCR - 0x4009 800C, U3LCR -
0x4009 C00C) bit description
Bit Symbol Value Description Reset Value
1:0 Word Length Select 00 5-bit character length 0
01 6-bit character length
10 7-bit character length
11 8-bit character length
2 Stop Bit Select 0 1 stop bit. 0
1 2 stop bits (1.5 if UnLCR[1:0]=00).
3 Parity Enable 0 Disable parity generation and checking. 0
1 Enable parity generation and checking.
5:4 Parity Select 00 Odd parity. Number of 1s in the transmitted character and the attached
parity bit will be odd.
0
01 Even Parity. Number of 1s in the transmitted character and the attached
parity bit will be even.
10 Forced "1" stick parity.
11 Forced "0" stick parity.
6 Break Control 0 Disable break transmission. 0
1 Enable break transmission. Output pin UARTn TXD is forced to logic 0
when UnLCR[6] is active high.
7 Divisor Latch
Access Bit (DLAB)
0 Disable access to Divisor Latches. 0
1 Enable access to Divisor Latches.
31:8 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
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