UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 736 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
The NVIC registers control interrupt handling. See Section 34.4.2 “Nested Vectored
Interrupt Controller” for more information.
34.3.1.5 Data types
The processor:
• supports the following data types:
– 32-bit words
– 16-bit halfwords
– 8-bit bytes
• supports 64-bit data transfer instructions.
• manages all data memory accesses as little-endian. See Section 34.3.2.1.
34.3.1.6 The Cortex Microcontroller Software Interface Standard
For a Cortex-M3 microcontroller system, the Cortex Microcontroller Software Interface
Standard (CMSIS) defines:
• a common way to:
– access peripheral registers
– define exception vectors
• the names of:
– the registers of the core peripherals
– the core exception vectors
• a device-independent interface for RTOS kernels, including a debug channel.
The CMSIS includes address definitions and data structures for the core peripherals in the
Cortex-M3 processor. It also includes optional interfaces for middleware components
comprising a TCP/IP stack and a Flash file system.
CMSIS simplifies software development by enabling the reuse of template code and the
combination of CMSIS-compliant software components from various middleware vendors.
Software vendors can expand the CMSIS to include their peripheral definitions and
access functions for those peripherals.
This document includes the register names defined by the CMSIS, and gives short
descriptions of the CMSIS functions that address the processor core and the core
peripherals.
Remark: This document uses the register short names defined by the CMSIS. In a few
cases these differ from the architectural short names that might be used in other
documents.
The following sections give more information about the CMSIS:
• Section 34.3.5.4
• Section 34.2.2 “Intrinsic functions”
• Section 34.4.2.1 “The CMSIS mapping of the Cortex-M3 NVIC registers”
• Section 34.4.2.10.1 “NVIC programming hints”.
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