UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 85 of 841
NXP Semiconductors
UM10360
Chapter 6: LPC176x/5x Nested Vectored Interrupt Controller (NVIC)
6.5.8 Interrupt Clear-Pending Register 1 register (ICPR1 - 0xE000 E284)
The ICPR1 register allows clearing the pending state of the second group of peripheral
interrupts, or for reading the pending state of those interrupts. Setting the pending state of
interrupts is done through the ISPR0 and ISPR1 registers (Section 6.5.5
and
Section 6.5.6
).
Table 59. Interrupt Set-Pending Register 1 register (ISPR1 - 0xE000 E204)
Bit Name Function
0 ICP_PLL1 PLL1 (USB PLL) Interrupt Pending clear.
Write: writing 0 has no effect, writing 1 changes the interrupt state to not pending.
Read: 0 indicates that the interrupt is not pending, 1 indicates that the interrupt is pending.
1 ICP_USBACT USB Activity Interrupt Pending clear. See functional description for bit 0.
2 ICP_CANACT CAN Activity Interrupt Pending clear. See functional description for bit 0.
31:3 - Reserved, user software should not write ones to reserved bits. The value read from a reserved bit
is not defined.
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