UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 70 of 841
NXP Semiconductors
UM10360
Chapter 5: LPC176x/5x Flash accelerator
5.2.2 Flash programming Issues
Since the flash memory does not allow accesses during programming and erase
operations, it is necessary for the flash accelerator to force the CPU to wait if a memory
access to a flash address is requested while the flash memory is busy with a
programming operation. Under some conditions, this delay could result in a Watchdog
time-out. The user will need to be aware of this possibility and take steps to insure that an
unwanted Watchdog reset does not cause a system failure while programming or erasing
the flash memory.
In order to preclude the possibility of stale data being read from the flash memory, the
LPC176x/5x flash accelerator buffers are automatically invalidated at the beginning of any
flash programming or erase operation. Any subsequent read from a flash address will
cause a new fetch to be initiated after the flash operation has completed.
5.3 Register description
The flash accelerator is controlled by the register shown in Table 48. More detailed
descriptions follow.
[1] Reset Value reflects the data stored in defined bits only. It does not include reserved bits content.
Table 48. Summary of flash accelerator registers
Name Description Access Reset
value
[1]
Address
FLASHCFG Flash Accelerator Configuration Register.
Controls flash access timing. See Table 49
.
R/W 0x303A 0x400F C000
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