UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 127 of 841
NXP Semiconductors
UM10360
Chapter 9: LPC176x/5x General Purpose Input/Output (GPIO)
9.5.3 GPIO port output Clear register FIOxCLR (FIO0CLR to FIO4CLR-
0x2009 C01C to 0x2009 C09C)
This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the FIOxSET register. Writing 0 has no effect. If any pin is
configured as an input or a secondary function, writing to FIOxCLR has no effect.
Access to a port pin via the FIOxCLR register is conditioned by the corresponding bit of
the FIOxMASK register (see Section 9.5.5
).
Aside from the 32-bit long and word only accessible FIOxCLR register, every fast GPIO
port can also be controlled via several byte and half-word accessible registers listed in
Table 108
, too. Next to providing the same functions as the FIOxCLR register, these
additional registers allow easier and faster access to the physical port pins.
Table 107. Fast GPIO port output Clear register (FIO0CLR to FIO4CLR- addresses 0x2009
C01C to 0x2009 C09C) bit description
Bit Symbol Value Description Reset
value
31:0 FIO0CLR
FIO1CLR
FIO2CLR
FIO3CLR
FIO4CLR
Fast GPIO output value Clear bits. Bit 0 in FIOxCLR controls pin
Px.0, bit 31 controls pin Px.31.
0x0
0 Controlled pin output is unchanged.
1 Controlled pin output is set to LOW.
Table 108. Fast GPIO port output Clear byte and half-word accessible register
description
Generic
Register
name
Description Register
length (bits)
& access
Reset
value
PORTn Register
Address & Name
FIOxCLR0 Fast GPIO Port x output
Clear register 0. Bit 0 in
FIOxCLR0 register
corresponds to pin Px.0 …
bit 7 to pin Px.7.
8 (byte)
WO
0x00 FIO0CLR0 - 0x2009 C01C
FIO1CLR0 - 0x2009 C03C
FIO2CLR0 - 0x2009 C05C
FIO3CLR0 - 0x2009 C07C
FIO4CLR0 - 0x2009 C09C
FIOxCLR1 Fast GPIO Port x output
Clear register 1. Bit 0 in
FIOxCLR1 register
corresponds to pin Px.8 …
bit 7 to pin Px.15.
8 (byte)
WO
0x00 FIO0CLR1 - 0x2009 C01D
FIO1CLR1 - 0x2009 C03D
FIO2CLR1 - 0x2009 C05D
FIO3CLR1 - 0x2009 C07D
FIO4CLR1 - 0x2009 C09D
FIOxCLR2 Fast GPIO Port x output
Clear register 2. Bit 0 in
FIOxCLR2 register
corresponds to pin Px.16 …
bit 7 to pin Px.23.
8 (byte)
WO
0x00 FIO0CLR2 - 0x2009 C01E
FIO1CLR2 - 0x2009 C03E
FIO2CLR2 - 0x2009 C05E
FIO3CLR2 - 0x2009 C07E
FIO4CLR2 - 0x2009 C09E
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