NXP Semiconductors LPC1768 - DMA Configuration Register (Dmacconfig - 0 X5000 4030); DMA Synchronization Register (Dmacsync - 0 X5000 4034)

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User manual Rev. 3 — 19 December 2013 600 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.5.13 DMA Configuration register (DMACConfig - 0x5000 4030)
The DMACConfig Register is read/write and configures the operation of the DMA
Controller. The endianness of the AHB master interface can be altered by writing to the M
bit of this register. The AHB master interface is set to little-endian mode on reset.
Table 557
shows the bit assignments of the DMACConfig Register.
31.5.14 DMA Synchronization register (DMACSync - 0x5000 4034)
The DMACSync Register is read/write and enables or disables synchronization logic for
the DMA request signals. The DMA request signals consist of the DMACBREQ[15:0],
DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0]. A bit set to 0 enables
the synchronization logic for a particular group of DMA requests. A bit set to 1 disables the
synchronization logic for a particular group of DMA requests. This register is reset to 0,
enabling synchronization logic by default. Table 558
shows the bit assignments of the
DMACSync Register.
Table 556. DMA Software Last Single Request register (DMACSoftLSReq - 0x5000 402C)
Bit Name Function
15:0 SoftLSReq Software last single transfer request flags for each of 16 possible sources. Each bit
represents one DMA request line or peripheral function:
0 - writing 0 has no effect.
1 - writing 1 generates a DMA last single transfer request for the corresponding
request line.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 557. DMA Configuration register (DMACConfig - 0x5000 4030)
Bit Name Function
0 E DMA Controller enable:
0 = disabled (default). Disabling the DMA Controller reduces power consumption.
1 = enabled.
1 M AHB Master endianness configuration:
0 = little-endian mode (default).
1 = big-endian mode.
31:2 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Table 558. DMA Synchronization register (DMACSync - 0x5000 4034)
Bit Name Function
15:0 DMACSync Controls the synchronization logic for DMA request signals. Each bit represents one
set of DMA request lines as described in the preceding text:
0 - synchronization logic for the corresponding DMA request signals are enabled.
1 - synchronization logic for the corresponding request line signals are disabled.
31:16 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.