UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 696 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.2.6.2 UMULL, UMLAL, SMULL, and SMLAL
Signed and Unsigned Long Multiply, with optional Accumulate, using 32-bit operands and
producing a 64-bit result.
34.2.6.2.1 Syntax
op{cond} RdLo, RdHi, Rn, Rm
where:
op is one of:
UMULL:
Unsigned Long Multiply.
UMLAL:
Unsigned Long Multiply, with Accumulate.
SMULL:
Signed Long Multiply.
SMLAL:
Signed Long Multiply, with Accumulate.
cond is an optional condition code, see Section 34.2.3.7 “
Conditional execution”.
RdHi, RdLo are the destination registers. For
UMLAL
and
SMLAL
they also hold the
accumulating value.
Rn, Rm are registers holding the operands.
34.2.6.2.2 Operation
The
UMULL
instruction interprets the values from Rn and Rm as unsigned integers. It
multiplies these integers and places the least significant 32 bits of the result in RdLo, and
the most significant 32 bits of the result in RdHi.
The
UMLAL
instruction interprets the values from Rn and Rm as unsigned integers. It
multiplies these integers, adds the 64-bit result to the 64-bit unsigned integer contained in
RdHi and RdLo, and writes the result back to RdHi and RdLo.
The
SMULL
instruction interprets the values from Rn and Rm as two’s complement signed
integers. It multiplies these integers and places the least significant 32 bits of the result in
RdLo, and the most significant 32 bits of the result in RdHi.
The
SMLAL
instruction interprets the values from Rn and Rm as two’s complement signed
integers. It multiplies these integers, adds the 64-bit result to the 64-bit signed integer
contained in RdHi and RdLo, and writes the result back to RdHi and RdLo.
34.2.6.2.3 Restrictions
In these instructions:
• do not use SP and do not use PC
• RdHi and RdLo must be different registers.
34.2.6.2.4 Condition flags
These instructions do not affect the condition code flags.
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