UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 792 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
For information about access permission, see Section 34.4.5.6.
34.4.5.5.1 SIZE field values
The SIZE field defines the size of the MPU memory region specified by the RNR. as
follows:
(Region size in bytes) = 2
(SIZE+1)
The smallest permitted region size is 32B, corresponding to a SIZE value of 4. Table 686
gives example SIZE values, with the corresponding region size and value of N in the
RBAR.
[1] In the RBAR, see Table 684.
Table 685. RASR bit assignments
Bits Name Function
[31:29] - Reserved.
[28] XN Instruction access disable bit:
0 = instruction fetches enabled
1 = instruction fetches disabled.
[27] - Reserved.
[26:24] AP Access permission field, see Table 689
.
[23:22] - Reserved.
[21:19, 17, 16] TEX, C, B Memory access attributes, see Table 687
.
[18] S Shareable bit, see Table 687
.
[15:8] SRD Subregion disable bits. For each bit in this field:
0 = corresponding sub-region is enabled
1 = corresponding sub-region is disabled
See Section 34.4.5.8.3
for more information.
Region sizes of 128 bytes and less do not support subregions.
When writing the attributes for such a region, write the SRD field as
0x00
.
[7:6] - Reserved.
[5:1] SIZE Specifies the size of the MPU protection region. The minimum
permitted value is 3 (b00010), see See Section 34.4.5.5.1
for more
information.
[0] ENABLE Region enable bit.
Table 686. Example SIZE field values
SIZE value Region size Value of N
[1]
Note
b00100 (4) 32B 5 Minimum permitted
size
b01001 (9) 1KB 10 -
b10011 (19) 1MB 20 -
b11101 (29) 1GB 30 -
b11111 (31) 4GB b01100 Maximum possible size
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