UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 789 of 841
NXP Semiconductors
UM10360
Chapter 34: Appendix: Cortex-M3 user guide
34.4.5.2 MPU Control Register
The MPU CTRL register:
• enables the MPU
• enables the default memory map background region
• enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and
FAULTMASK escalated handlers.
See the register summary in Table 680
for the MPU CTRL attributes. The bit assignments
are shown in Table 682
.
When ENABLE and PRIVDEFENA are both set to 1:
[15:8] DREGION Indicates the number of supported MPU data regions:
0x08
= Eight MPU regions.
[7:0] - Reserved.
[0] SEPARATE Indicates support for unified or separate instruction and
date memory maps:
0 = unified.
Table 681. TYPE register bit assignments …continued
Bits Name Function
Table 682. MPU CTRL register bit assignments
Bits Name Function
[31:3] - Reserved.
[2] PRIVDEFENA Enables privileged software access to the default memory map:
0 = If the MPU is enabled, disables use of the default memory map.
Any memory access to a location not covered by any enabled
region causes a fault.
1 = If the MPU is enabled, enables use of the default memory map
as a background region for privileged software accesses.
When enabled, the background region acts as if it is region number
-1. Any region that is defined and enabled has priority over this
default map.
If the MPU is disabled, the processor ignores this bit.
[1] HFNMIENA Enables the operation of MPU during hard fault, NMI, and
FAULTMASK handlers.
When the MPU is enabled:
0 = MPU is disabled during hard fault, NMI, and FAULTMASK
handlers, regardless of the value of the ENABLE bit
1 = the MPU is enabled during hard fault, NMI, and FAULTMASK
handlers.
When the MPU is disabled, if this bit is set to 1 the behavior is
Unpredictable.
[0] ENABLE Enables the MPU:
0 = MPU disabled
1 = MPU enabled.
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