UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 573 of 841
NXP Semiconductors
UM10360
Chapter 28: LPC176x/5x Watchdog Timer (WDT)
28.4.2 Watchdog Timer Constant register (WDTC - 0x4000 0004)
The WDTC register determines the time-out value. Every time a feed sequence occurs
the WDTC content is reloaded in to the Watchdog timer. It’s a 32-bit register with 8 LSB
set to 1 on reset. Writing values below 0xFF will cause 0x0000 00FF to be loaded to the
WDTC. Thus the minimum time-out interval is T
WDCLK
256 4.
28.4.3 Watchdog Feed register (WDFEED - 0x4000 0008)
Writing 0xAA followed by 0x55 to this register will reload the Watchdog timer with the
WDTC value. This operation will also start the Watchdog if it is enabled via the WDMOD
register. Setting the WDEN bit in the WDMOD register is not sufficient to enable the
Watchdog. A valid feed sequence must be completed after setting WDEN before the
Watchdog is capable of generating a reset. Until then, the Watchdog will ignore feed
errors. After writing 0xAA to WDFEED, access to any Watchdog register other than writing
0x55 to WDFEED causes an immediate reset/interrupt when the Watchdog is enabled.
The reset will be generated during the second PCLK following an incorrect access to a
Watchdog register during a feed sequence.
28.4.4 Watchdog Timer Value register (WDTV - 0x4000 000C)
The WDTV register is used to read the current value of Watchdog timer.
When reading the value of the 32-bit timer, the lock and synchronization procedure takes
up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual
value of the timer when it's being read by the CPU.
28.4.5 Watchdog Timer Clock Source Selection register (WDCLKSEL -
0x4000 0010)
This register allows selecting the clock source for the Watchdog timer. The possibilities are the
Internal RC oscillator (IRC) or the APB peripheral clock (pclk). The function of bits in WDCLKSEL
are shown in
Table 528. The clock source selection can be locked by software, so that it cannot be
modified. On reset, the clock source selection bits are always unlocked.
When the IRC is chosen as the watchdog clock source, the watchdog timer can remain
running in deep sleep mode, and can reset or wake up the device from that mode.
Table 525: Watchdog Constant register (WDTC, address 0x4000 0004) bit description
Bit Symbol Description Reset Value
31:0 Count Watchdog time-out interval. 0x0000 00FF
Table 526: Watchdog Feed register (WDFEED, address 0x4000 0008) bit description
Bit Symbol Description Reset
Value
7:0 Feed Feed value should be 0xAA followed by 0x55. NA
31:8 - Reserved, user software should not write ones to reserved bits. The
value read from a reserved bit is not defined.
NA
Table 527: Watchdog Timer Value register (WDTV, address 0x4000 000C) bit description
Bit Symbol Description Reset Value
31:0 Count Counter timer value. 0x0000 00FF
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