NXP Semiconductors LPC1768 - PWM Timer Control Register (PWM1 TCR 0 X4001 8004); PWM Count Control Register (PWM1 CTCR - 0 X4001 8070)

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 517 of 841
NXP Semiconductors
UM10360
Chapter 24: LPC176x/5x Pulse Width Modulator (PWM)
24.6.2 PWM Timer Control Register (PWM1TCR 0x4001 8004)
The PWM Timer Control Register (PWMTCR) is used to control the operation of the PWM
Timer Counter. The function of each of the bits is shown in Table 447
.
24.6.3 PWM Count Control Register (PWM1CTCR - 0x4001 8070)
The Count Control Register (CTCR) is used to select between Timer and Counter mode,
and in Counter mode to select the pin and edge(s) for counting. The function of each of
the bits is shown in Table 448
.
9 PWMMR5 Interrupt Interrupt flag for PWM match channel 5. 0
10 PWMMR6 Interrupt Interrupt flag for PWM match channel 6. 0
31:11 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
NA
Table 446: PWM Interrupt Register (PWM1IR - address 0x4001 8000) bit description …continued
Bit Symbol Description Reset
Value
Table 447. PWM Timer Control Register (PWM1TCR address 0x4001 8004) bit description
Bit Symbol Value Description Reset
Value
0 Counter Enable 1 The PWM Timer Counter and PWM Prescale Counter are enabled for counting. 0
0 The counters are disabled.
1 Counter Reset 1 The PWM Timer Counter and the PWM Prescale Counter are synchronously reset
on the next positive edge of PCLK. The counters remain reset until this bit is
returned to zero.
0
0 Clear reset.
2 - Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA
3 PWM Enable 1 PWM mode is enabled (counter resets to 1). PWM mode causes the shadow
registers to operate in connection with the Match registers. A program write to a
Match register will not have an effect on the Match result until the corresponding bit
in PWMLER has been set, followed by the occurrence of a PWM Match 0 event.
Note that the PWM Match register that determines the PWM rate (PWM Match
Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a
Match event will not occur to cause shadow register contents to become effective.
0
0 Timer mode is enabled (counter resets to 0).
31:4 - Reserved, user software should not write ones to reserved bits. The value read
from a reserved bit is not defined.
NA