NXP Semiconductors LPC1768 - Using the DMA Controller; Programming the DMA Controller; Enabling the DMA Controller; Disabling the DMA Controller

UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 608 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
31.6 Using the DMA controller
31.6.1 Programming the DMA controller
All accesses to the DMA Controller internal register must be word (32-bit) reads and
writes.
31.6.1.1 Enabling the DMA controller
To enable the DMA controller set the Enable bit in the DMACConfig register.
31.6.1.2 Disabling the DMA controller
To disable the DMA controller:
• Read the DMACEnbldChns register and ensure that all the DMA channels have been
disabled. If any channels are active, see Disabling a DMA channel.
• Disable the DMA controller by writing 0 to the DMA Enable bit in the DMACConfig
register.
31.6.1.3 Enabling a DMA channel
To enable the DMA channel set the channel enable bit in the relevant DMA channel
configuration register. Note that the channel must be fully initialized before it is enabled.
31.6.1.4 Disabling a DMA channel
A DMA channel can be disabled in three ways:
• By writing directly to the channel enable bit. Any outstanding data in the FIFO’s is lost
if this method is used.
• By using the active and halt bits in conjunction with the channel enable bit.
• By waiting until the transfer completes. This automatically clears the channel.
Disabling a DMA channel and losing data in the FIFO
Clear the relevant channel enable bit in the relevant channel configuration register. The
current AHB transfer (if one is in progress) completes and the channel is disabled. Any
data in the FIFO is lost.
Disabling the DMA channel without losing data in the FIFO
• Set the halt bit in the relevant channel configuration register. This causes any future
DMA request to be ignored.
• Poll the active bit in the relevant channel configuration register until it reaches 0. This
bit indicates whether there is any data in the channel that has to be transferred.
• Clear the channel enable bit in the relevant channel configuration register
31.6.1.5 Setting up a new DMA transfer
To set up a new DMA transfer:
If the channel is not set aside for the DMA transaction: