EasyManua.ls Logo

NXP Semiconductors LPC1768 - Page 359

NXP Semiconductors LPC1768
841 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 19 December 2013 359 of 841
NXP Semiconductors
UM10360
Chapter 16: LPC176x/5x CAN1/2
5 EPI 0 (reset)
1 (set)
Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the
CAN controller switches between Error Passive and Error Active mode in either
direction.
This is the case when the CAN Controller has reached the Error Passive Status
(at least one error counter exceeds the CAN protocol defined level of 127) or if
the CAN Controller is in Error Passive Status and enters the Error Active Status
again.
00
6 ALI 0 (reset)
1 (set)
Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the
CAN controller loses arbitration while attempting to transmit. In this case the
CAN node becomes a receiver.
00
7 BEI 0 (reset)
1 (set)
Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN
controller detects an error on the bus.
0X
8 IDI 0 (reset)
1 (set)
ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN
Identifier has been received (a message was successfully transmitted or
aborted). This bit is set whenever a message was successfully transmitted or
aborted and the IDIE bit is set in the IER register.
00
9 TI2 0 (reset)
1 (set)
Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to
1 (whenever a message out of TXB2 was successfully transmitted or aborted),
indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.
00
10 TI3 0 (reset)
1 (set)
Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to
1 (whenever a message out of TXB3 was successfully transmitted or aborted),
indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.
00
15:11 - - Reserved, user software should not write ones to reserved bits. 0 0
Table 320. CAN Interrupt and Capture Register (CAN1ICR - address 0x4004 400C, CAN2ICR - address 0x4004 800C)
bit description …continued
Bit Symbol Value Function Reset
Value
RM
Set

Table of Contents

Other manuals for NXP Semiconductors LPC1768

Related product manuals