NXP Semiconductors LPC1768 - Page 595

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User manual Rev. 3 — 19 December 2013 595 of 841
NXP Semiconductors
UM10360
Chapter 31: LPC176x/5x General Purpose DMA (GPDMA)
[1] Bit 17 of this register is a read-only status flag.
DMACC2Config DMA Channel 2 Configuration Register R/W 0
[1]
0x5000 4150
Channel 3 registers
DMACC3SrcAddr DMA Channel 3 Source Address Register R/W 0 0x5000 4160
DMACC3DestAddr DMA Channel 3 Destination Address Register R/W 0 0x5000 4164
DMACC3LLI DMA Channel 3 Linked List Item Register R/W 0 0x5000 4168
DMACC3Control DMA Channel 3 Control Register R/W 0 0x5000 416C
DMACC3Config DMA Channel 3 Configuration Register R/W 0
[1]
0x5000 4170
Channel 4 registers
DMACC4SrcAddr DMA Channel 4 Source Address Register R/W 0 0x5000 4180
DMACC4DestAddr DMA Channel 4 Destination Address Register R/W 0 0x5000 4184
DMACC4LLI DMA Channel 4 Linked List Item Register R/W 0 0x5000 4188
DMACC4Control DMA Channel 4 Control Register R/W 0 0x5000 418C
DMACC4Config DMA Channel 4 Configuration Register R/W 0
[1]
0x5000 4190
Channel 5 registers
DMACC5SrcAddr DMA Channel 5 Source Address Register R/W 0 0x5000 41A0
DMACC5DestAddr DMA Channel 5 Destination Address Register R/W 0 0x5000 41A4
DMACC5LLI DMA Channel 5 Linked List Item Register R/W 0 0x5000 41A8
DMACC5Control DMA Channel 5 Control Register R/W 0 0x5000 41AC
DMACC5Config DMA Channel 5 Configuration Register R/W 0
[1]
0x5000 41B0
Channel 6 registers
DMACC6SrcAddr DMA Channel 6 Source Address Register R/W 0 0x5000 41C0
DMACC6DestAddr DMA Channel 6 Destination Address Register R/W 0 0x5000 41C4
DMACC6LLI DMA Channel 6 Linked List Item Register R/W 0 0x5000 41C8
DMACC6Control DMA Channel 6 Control Register R/W 0 0x5000 41CC
DMACC6Config DMA Channel 6 Configuration Register R/W 0
[1]
0x5000 41D0
Channel 7 registers
DMACC7SrcAddr DMA Channel 7 Source Address Register R/W 0 0x5000 41E0
DMACC7DestAddr DMA Channel 7 Destination Address Register R/W 0 0x5000 41E4
DMACC7LLI DMA Channel 7 Linked List Item Register R/W 0 0x5000 41E8
DMACC7Control DMA Channel 7 Control Register R/W 0 0x5000 41EC
DMACC7Config DMA Channel 7 Configuration Register R/W 0
[1]
0x5000 41F0
Table 544. GPDMA register map
Name Description Access Reset
state
Address