UM10360 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2013. All rights reserved.
User manual Rev. 3 — 20 December 2013 2 of 841
NXP Semiconductors
UM10360
LPC17xx user manual
Revision history
Rev Date Description
3 20131220 LPC176x/5x user manual
Modifications:
• Part ID for part LPC1763 added.
• Changed title to “LPC176x/5x User manual”.
• Updated numbering for CAN interfaces: CAN1 uses SCC = 0, CAN2 uses SCC = 1. See
Section 16.13 “ID look-up table RAM” and Section 16.15 “Configuration and search algorithm”.
• Updated Serial Wire Output description (Table 609).
• Clarified burst mode information for ADGINTEN (Table 531 and Table 533).
• Condition CCLK > 18 MHz for USB operation is not applicable for this USB peripheral and was
removed (see Section 4.7.1
, Section 11.13, and Section 13.11).
• Description of CAN interrupt request updated. One common CAN interrupt is triggered. See
Section 16.8.3.
• Condition on minimum frequency of CAP input clock added in Section 21.5.1.
• Description of RIMASK register corrected. See Table 43 3.
• Condition for maximum allowable STCLK frequency added. See Section 23.4.
• Delete statement “All PWM related Match registers are configured for toggle on match.” in
Figure 120.
• Description of INXCNT register updated. See Section 26.6.3.6.
• Reset value of the RTC_AUX register corrected. See Table 507.
• DAC power-down mode removed in Section 30.2.
• Added: The DAC output is disabled in deep-sleep, power-down, or deep power-down modes.
See Table 537
.
• Boot loader SRAM use explained. See Section 33.5.
• SYSRESETREQ supported. See Table 659.
• Figure 18 “Ethernet packet fields” corrected.
• Bit description in the SPI test control register corrected. Bit 0 indicates test mode. All other bits
are reserved. See Section 17.7.5 “SPI Test Control Register (SPTCR - 0x4002 0010)”.
• Figure 117 “RI timer block diagram” updated.
2 20100819 LPC176x/5x user manual revision.
Modifications:
• UART0/1/2/3: FIFOLVL register removed.
• ADC: reset value of the ADCTRM register changed to 0xF00 (Table 500).
• Timer0/1/2/3: Description of DMA operation updated.
• USB Device: Corrected error in the USBCmdCode register (0x01 = write, 0x02 = read)
(Table 184).
• Clocking and power control: add bit 15 (PCGPIO) to PCONP register (Table 46).
• Part LPC1763 added.
• Update register bit description of USBIntStat register in Host and Device mode (Table 155 and
Table 221).
• Motor control PWM: update description of match and limit registers.
• GPIO: update register bit description of the FIOPIN register (Table 73).
• Numerous editorial updates throughout the user manual.
To Next Page
Loading...
Need help?
General
