(6) EEPROM
(Q9)
This
256-bit
serial data electrically erasable and programmable ROM stores the menu mode
data.
(7)
LSI
(MSM79H097)
(46)
The MSM79H097 controls the DMA, head drive and LF microstep. The details are described
below.
(a) DMA control
Data transfers from ROM to D-RAM or between
D-RAMS
is performed by DMA transfer
eliminating the need of the CPU to perform such operations.
By setting the address of the transfer origin, the transfer destination and the number of
bytes to be transferred and starting from the CPU, data in memory can be transferred
directly.
(b)
Head drive control
Drive pulses are produced for impact timing of the head using IPT signals as triggers. IPT
signals are generated by phase A and
B
signals from the spacing motor.
The pulse width of this drive differs according to the number of the impact pins.
Its duration
can be preset by the CPU.
(c)
Print data transfer control
Performs the serial transfer control of print data.
Print data will be transferred automatically from the memory area stored for decoding to
the register in this LSI in synchronization with an IPT signal coming from MSM6990.
The data which is stored in the register will be transferred to the head drive unit as serial
data just before the next impact timing.
(d)
LF micro step control
Performs micro step control to enable fine feed of the LF motor.
(e)
Memory interface
This function expands the memory space for ROMs and
RAMS
which are connected to this
LSI,
and makes it possible for the memory to access 368 Kbytes.
(0 D-RAM refresh
Performs refreshing of D-RAMS using the CAS before RAS refresh method.
3-3
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