Onkyo DV-SP301 - Page 43

DV-SP301
IC TERMINAL DESCRIPTION
106 AUX_CLK Auxiliary clock out I/O
107 VDD3_3 3.3 V power supply Power
108 VSS Ground Power
109
TRST
5
Test reset I
110 TMS Test mode select I
111 TDO Test data out O
112 TDI Test data in I
113 TCK Test clock I
114 PWM2 Pulse Width Modulator 2
ODDEVEN
6
I/O
115 PWM1 Pulse Width Modulator 1
BOOT_FROM_ROM
7
I/O
116 PWM0 Pulse Width Modulator 0 HSYNC I/O
117 CPU_OE Output enable I/O
118 CPU_PROCLK EMI clock O
119 VDD1_8 1.8V power supply Power
120 PIX_CLK 27 MHz main clock I
121 VSS Ground Power
122 VDD_PLL VDD PLL=1.8V Power
123 VSS_PLL GND PLL=GND Power
124 RESET Chip reset I
125 IRQ[2] IRQ[2] (MD_IRQ) I
126 IRQ[1] IRQ[1] (ATAPI IRQ) I
127 IRQ[0] IRQ[0] (SERVO_IRQ) I
128 CPU_BE[0] Byte 0 enable DQM[0] O
129 CPU_BE[1] Byte 1 enable DQM[1] O
130 CPU_RW Read-not-write NOT_SDRAM_WE O
131 CPU_WAIT Wait state I
132 CPU_CE[3] Chip select bank 3 CS_SUB_BANK3 O
133 CPU_CE[2] Chip select bank 2 O
134 CPU_CE[1] Chip select bank 1 O
135 CPU_CE[0] DRAM RAS 0 SDRAM_RAS O
136 VDD3_3 3.3 V power supply Power
137 VSS Ground Power
138 CPU_RAS1 DRAM RAS 1 NOT_SDRAM_CS1 I/O
Pin
number
Pin name Main function
Alternate function
Pin
type
Input Outp
ut
PIN LIST SORTED BY FUNCTION 5