Onkyo HT-R960 - Page 63

TX-SR606
IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-32
Q8162 : SiI9185ACTU (Three Input, Single Output Deep Color HDMI Switch)-1/3
BLOCK DIAGRAM
PIN LAYOUT
Configuration
Logic
EDID
RAM
I C Switch
2
Serializer /
Tx Driver
TX0+/-
CEC/ IF
HPD Switch5V Switch
PLL
Oversample
Termination /
Equalizer
TX1+/-
TXC+/-
TX2+/-
HPDIN
DPLL
R0X0+/-
R0X1+/-
R0X2+/-
R0XC+/-
R1X0+/-
R1X1+/-
R1X2+/-
R1XC+/-
R2X0+/-
R2X1+/-
R2X2+/-
R2XC+/-
DSCL2 DSDA2 DSCL1 DSDA1 DSCL0 DSDA0 TSCL TSDA LSCL / EPSEL[1] LSDA / EPSEL[0]
RPWR0
RPWR1 RPWR2
TPWR /
I2CADDR
HPD0 HPD2 HPD1
CEC_A
CEC_D
Serializer /
Tx Driver
Serializer /
Tx Driver
Clock Gen /
Tx Driver
SiI9185
80-pin TQFP
(Top View)
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
AGND
R0C+
R0C-
AVCC18
HPD0
DGND
DVCC
RESET#
TPWR / 12CADDR
TX2+
TX2-
AGND
TX1+
TX1-
AVCC18
TX0+
TX0-
AGND
TXC+
TXC-
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
R2X0-
R2X0+
AVCC33
R2X1-
R2X1+
AGND
R2X2-
R2X2+
AVDD18
DSDA2
DSCL2
RPWR2
LSDA
LSCL
RSVD
HPDIN
TSDA
TSCL
AGND
EXTSWING
R1X0-
R1X0+
AVCC33
R1X1-
R1X1+
AGND
R1X2-
R1X2+
AVDD18
DSDA1
DSCL1
RPWR1
DVCC
DGND
EXTPSEL
HPD2
AVCC18
RXC2-
RXC2+
AGND
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
AGND R1C+ R1C- AVCC18 HPD1 VAUX33 CEC_A CEC_D RPWR0 DSCL0 DSDA0 AVDD18 R0X2+ R0X2- AGND R0X1+ R0X1- AVCC33 R0X0+ R0X0-
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
Termination /
Equalizer
Termination /
Equalizer